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| MC33561 Product Preview Power Management and Interface IC for Smartcard Readers and Couplers The MC33561 is an integrated circuit dedicated to the Smartcard interface applications. The device handles any type of smart or memory based card through a simple and flexible microcontroller interface. On top of that, thanks to the built-in chip select pin, several couplers can be connected in parallel. The MC33561 is particularly suited for low cost, low power applications, with high extended battery life coming from extremely low quiescent current. Features http://onsemi.com 20 * 100% Compatible with ISO 7816-3 Standard * Wide Battery Supply Voltage Range: 1.8 VtVbat V * Programmable VCC Supply to Cope with either 3 V or 5 V Card t6.6 1 TSSOP-20 DTB SUFFIX CASE 948E PIN CONNECTIONS PWR_GND PWR_ON RDY_MOD CS RESET I/O SYN_CLK ASYN_CLK INT 1 2 3 4 5 6 7 8 9 10 Preliminary Pinout 20 19 18 17 16 15 14 13 12 11 +VBAT Lout CRD_DET CRD_CLK CRD_RST CRD_VCC CRD_GND CRD_IO DIG_GND * * * * * * * Operation Very Low Quiescent Current in Standby Mode: 5 A Max Built-in DC/DC Converter Generates the VCC Supply with Minimum External Components Full Control of the Power Up/Down Sequence Yields High Signal Integrity on both the Card I/O and the Signal Lines Programmable Card Clock Generator Built-in Chip Select Logic Allows Parallel Coupling Operation ESD Protection on Card Pins (4 kV, Human Body Model) Fault Monitoring Includes Vbatlow, Vcclow and Icclim +5V GND 4 MHz GND ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. 40 OSC2 IRQ OSC1 TCAP RST PD0/RDI PD1/TDO PD2/MISO PD3/MOSI PD4/SCK 2 41 39 1 31 32 33 34 35 GND 30 29 28 26 25 1 2 3 4 5 6 7 8 9 RESET 1 2 +5 GND GND 3 4 5 6 7 8 9 Card Detection CLK RST VCC GND I/O MC33561 20 19 18 17 16 15 14 13 12 11 + 5 9 4 8 3 7 2 6 1 RS232 16 GND 13 2 3 1 MAX202 12 PC0 PC1 PC2 PC3 PC4 MC68HC705C9ACB(42) 7 10 PWR_GND VBAT PWR_ON Lout RDY_MOD CRD_DET CS CRD_CLK RESET I/O CRD_RST SYN_CLK CRD_VCC ASY_CLKIN CRD_GND CRD_IO INT DIG_GND CARD SLOT 15 6 5 4 Figure 1. Typical Application Diagram This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. GND (c) Semiconductor Components Industries, LLC, 1999 1 November, 1999 - Rev. 0 Publication Order Number: MC33561/D MC33561 +VBAT 20 VBAT_OK R1 D1 GND 17 11 R2 50 k +VBAT GND R3 RDY_MOD 3 50 k Q1 VBAT_OK POWER MANAGEMENT LOGIC AND PROGRAMMING GND CRD_DET DIG_GND +VBAT +VBAT INT 9 +VBAT 50 k CS PWRON 4 2 PROGRAM CARD_ENABLE GND FAULT ON/OFF 3V/5V +VBAT DC/DC CONVERTER CARD PINS SEQUENCER SEQ 1 SEQ 2 SEQ 3 SEQ 4 GND CRD_VCC BIDIRECTIONAL I/O I/O 6 12 CRD_I/O GND 19 14 R6 IR Lout CRD_VCC 1 PWR_GND +VBAT RESET 5 R5 100 k GND SYN_CLK 7 R4 100 k GND ASYN_CLK 8 PROGRAM SEQ 2 CLOCK GENERATOR AND PROGRAMMING CARD_ENABLE DATA LATCH SEQ 4 +VBAT LEVEL SHIFT CRD_VCC CRD_RST 15 CRD_VCC LEVEL SHIFT 16 13 GND CRD_CLK CRD_GND Figure 2. Detailed Block Diagram http://onsemi.com 2 MC33561 Table 1. Pin Functions and Description CONTROLLER INTERFACE Pin 2 3 Symbol PWR_ON RDY_MOD Type INPUT Pull Down I/O and Pull Up Name/Function This pin valid the operation of the internal DC/DC converter. This bidirectional pin features tri-state output and schmitt trigger input. When RDY_MOD is forced to 0, the MC33xxx is set to programming mode by a negative transition on CS pin. This pin provides the MC33561 chip select function. Pins x x x are disabled when CS = H. When RDY_MOD = L, the device jumps in the programming mode upon the falling edge of CS (See Figure YY). The signal presents as this pin is translated to pin XX (card reset signal) when CS = L. The signal on this pin is latched when CS = H. This pin is also used in programming mode (See ZZZ). This pin is connected to an external microcontroller interface. A bidirectional level translator adapts the serial I/O signal between the smartcard and the microcontroller. The level translator is enabled when CS = L. The signal present on this pin is latched when CS = H. This pin is also used in programming mode (See ZZZ). This pin, generally connected to the controller serial interface clock, is used to set up communications with synchronous cards. The signal is fed to the internal clock selector circuit and is translated to CRD_CLK upon appropriate programming of the MC33561. When the device operates in the programming mode, the signal presents on this pin is latched when CS = H. This pin can be connected to either the microcontroller master clock, or to any clock signal, to drive the asynchronous cards. The signal is fed to internal clock selector circuit and translated to the CRD_CLK at either the same frequency, or divided by 2 or 4, depending upon the programming mode (See AAA). This pin is activated LOW when a card has been inserted and detected by the interface. The signal is reset to a logic 1 on the rising edge of either CS or PWR_ON. The Collector open mode makes possible the wired AND/OR external logic. When two or more interfaces share the INT function with a single micro controller, the software must polls the MC33561 to identify the origin of the interupt. 4 CS INPUT Pull Up INPUT Pull Down Input/Output 5 RESET 6 I/O 7 SYN_CLK CLOCK INPUT Pull Down 8 ASY_CLK_IN CLOCK INPUT High Impedance 9 INT OUTPUT Pull Down CARD INTERFACE 12 CRD_IO I/O This pin handles the connection to the serial I/O pin of the card connector. A bi-directional level translator adapts the serial I/O signal between the card and the micro controller. This pin is connected to the external card ground. It is the ground reference for all analog and digital signals. This pin provides the power to the external card. It is the logic level "1" for CRD_IO, CRD_RST and CRD_CLK signals. This pin is connected to the RESET pin of the card connector. A level translator adapts the RESET signal from the micro controller to the external card. This pin is connected to the CLK pin of the card connector. The CRD_CLK signal comes from the clock selector circuit output. The clock selection is programmed by using pins x x x with RDY_MOD forced to a logic zero. The signal coming from the external card connector is used to detect the presence of the card. A built in pull up resistor makes this pin active LOW. 13 14 15 16 CRD_GND CRD_VCC CRD_RST CRD_CLK GROUND POWER OUTPUT OUTPUT 17 CRD_DET INPUT http://onsemi.com 3 MC33561 Pin Symbol Type Name/Function POWER SUPPLY AND GROUND 1 13 14 19 20 PWR_GND CRD_GND CRD_VCC Ext_L Vbat POWER POWER POWER POWER POWER This pin is the current return from the external inductor L1. It is mandatory to carefully connect this pin to CRD_GND ground plane. This pin is the signal ground and must be connected to the ground pin of the card connector. This pin is the reference level for all analog and digital signals. This pin is connected to the Vcc pin of the card connector. This pin is the logic level reference for pins xx xx xx. This pin is connected to the external inductor used for the DC/DC converter. Please refer to the DC/DC block description. This pin is connected to the supply voltage. The MC33561 operation is inhibited when Vbat is below the minimum value. http://onsemi.com 4 MC33561 Programming and Status Functions The MC33561 features a programming interface and a status interface. Table 2 illustrates the programming mode. Table 2. Programming and Status Functions Pin Out Logic Program CRD_VCC to 3 V/5 V RDY_MOD (In-out) CS (in) PWR_ON (in) RESET (in) I/O (in) Force to 0 Rising edge 0/1 Program CLK input/divide ratio Program CLK input/divide ratio Select Vcc ON/OFF READ 0 0/1 Not used Not used Select Clock Input Force to 0 Rising edge Program CRD_VCC 0/1 0/1 Program ASY_CLKIN Divide Ration Force to 0 Rising edge Program CRD_VCC 0/1 0/1 Poll Card Status READ 0 0 or Hi-Z Not used Not used Poll CRD_VCC Status READ 0 1 Not used Not used MAXIMUM RATINGS(1) Symbol Vbat Ibat VCC ICC Vin Iin Vout Iout Vcard Icard IL Card Interface Pins Inductor Driver Pin Power Ground Pin (Pin 1) ESD Capability(2) Standard Pins Card Interface Pins SO-16WB Package Power Dissipation @ Tamb = +85C Thermal Resistance Junction to Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature(3) Storage Temperature Range Digital Output Pins Battery Supply Voltage Battery Supply Current Power Supply Voltage Power Supply Current Digital Input Pins Rating Value Unit V mA V mA V mA V mA V mA mA mA kV kV mW C/W C C C C "200 "150 *0.5 V t Vin t Vbat +0.5 V, but t 7.0 "5.0 *0.5 V t Vin t Vbat +0.5 V, but t 7.0 "10 *0.5 V t Vcard t Vcc +0.5 V, "25 "200 "100 2 4 285 140 6.0 7.0 VESD PD RJA TA TJ TJmax Tsg *25 to +85 *40 to +125 *65 to +150 +150 (1) Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25C. (2) Human Body Model, R = 1500 , C = 100 pF (3) Absolute Maximum Rating beyond which damage to the device may occur. http://onsemi.com 5 MC33561 ELECTRICAL CHARACTERISTICS The convention considers current flowing into the pin (sink current) as positive and current flowing out of the pin (source current) as negative. (Conditions: VBAT = 4 V, VCC = 5 V nom, PWR_ON = VBAT , -ICC = 10 mA, -25C TA 85C, L1 = 47 H, CRD_VCC capacitor = 10 F, unless otherwise noted.) BATTERY POWER SUPPLY SECTION Symbol Vbat Iobat Characteristic Supply Voltage Range Standby Quiescent Current Test Conditions Normal Operating Range Extended Operating Range(4) PWR_ON = GND, CRDC_ON = GND ASY_CLKIN = GND, Vbat = 6 V, all other logic inputs and outputs open Min 2.2 1.8 -- Typ -- -- -- Max 6.0 6.6 5.0 Unit V A Ibatop DC Operating Current Vbat Under Voltage Detection Upper Voltage Lower Voltage Hysteresis *ICC = 10 mA, Vcc = 5 V, Vbat = 6 V -- -- -- 1.6 1.4 0.2 12.5 -- A V (4) See Figures x and xx. POWER SUPPLY SECTION @ Vcc = 5 V Nominal Symbol Vcc Characteristic Output Voltage Test Conditions 2.2 V 1 mA 3.0 V 1 mA t Vbat t6 V t*ICC t 25 mA tVbat t6 V t*ICC t 60 mA Min 4.75 4.60 Typ 5.0 5.0 Max 5.25 5.40 Unit V *ICCLim tdy ICCst Vth Vtl Vhyss Card Vcc Under Voltage Detection Upper Threshold Lower Threshold Switching Hysteresis Peak Output Current Current Limit Time Out Start-up Current RDY_MOD Output See Table 4 4.2 120 VCC = 4 V, Internally Limited RDY_MOD = L VCC = 4 V 70 -- 70 50 -- -- -- 70 4.5 180 -- 160 -- -- 100 400 120 -- Vcc-0.14 V V mV mA ms mA -- -- -- -- 160 520 -- -- tCCA t +85C T *40C t TA t 0C 0C IL = 50 mA IL = 50 mA TA = +25C PWR_ON = GND VCC = 2 V V =2V Vsat VF FSW ISD Low Side Power Switch Saturation Rectifier Forward Voltage DC/DC Switching Frequency Shut Down Current (Card Access Deactivated) mV mV kHz mA POWER SUPPLY SECTION @ Vcc = 3 V Nominal Symbol Vcc Characteristic Output Voltage Test Conditions 2.2 V 1 mA 2.5 V 1 mA t Vbat t6 V t*ICC t 10 mA tVbat t6 V t*ICC t 50 mA Min 2.75 2.60 Typ 3.0 3.0 Max 3.25 3.40 Vcc-0.10 Unit V Vth Vtl Vhyss ICCst ISD Card Vcc Under Voltage Detection Upper Threshold Lower Threshold Switching Hysteresis Start-up Current Shut Down Current RDY_MOD Output See Table yyy 2.4 80 2.7 110 -- -- V V mV mA -- -- tCCA t +85C T *40C t TA t 0C 0C V =2V 50 50 http://onsemi.com 6 MC33561 APPLICATION INTERFACE DC SECTION @ Vbat = 5 V Symbol VIH VIL Characteristic Input High Threshold Voltage (Increasing) Input Low Threshold Voltage (Decreasing) Switching Hysteresis Threshold Voltage Rdown Rup VOH Pull-down Resistance Pull-up Resistance Output High Voltage Test Conditions Pin Pin Pin Pin Pin Pin Vin = Vbat Min 0.55*Vbat 0.3*Vbat 0.2*Vbat 0.3*Vbat 0.06*Vbat Typ -- -- Max 0.55*Vbat 0.45*Vbat 0.40*Vbat 0.50*Vbat 0.30*Vbat -- 200 200 -- Unit V V Vhyst -- -- 100 100 -- V V k k V *1 V -- 50 50 Vbat A, @ CS = H IOH = A IOH = mA, Output Mode IOH = IOL = 1 mA IOL = 0.2 mA Vin = 2.5 V, CS = H *2.5 *50 *0.2 Vin = 0.5 V *1 VOL Ileak Output Low Voltage Input Leakage Current -- -- -- -- 0.4 2.0 V A CARD INTERFACE DC SECTION @ Vbat = 5 V Symbol VOH VOL Characteristic Output High Voltage Output Low Voltage I/O Pull-up Resistance, Operating Mode, CS = L, PWR_ON = H Vsec Card Pins Security Voltage (Card Access Deactivated) Test Conditions IOH = A IOL = 0.2 mA IOL = 1 mA IOL = 0.2 mA VOL = 0.5 V *20 Min Vcc-0.9 -- 18 Typ -- -- -- Max -- 0.4 -- Unit V V k PWR_ON = GND, Iin = 10 mA -- -- 2.0 V DIGITAL DYNAMIC SECTION @ Vbat = 5 V, Normal Operating Mode(6) Symbol Fasyclk Fcrdclk Rclk Trclk Tfclk Fio Trio Tfio Characteristic Input Clock Frequency Card Clock Frequency Card Clock Duty Cycle(7) Card Clock Rise/Fall Time I/O Data Transfer Frequency I/O Rise and Fall Time I/O Transfer Time Tdseq Tdres Tdrdy Twon Card Signal Sequence Interval Internal Reset Delay Ready Delay Time PWR_ON Low Pulse Width CS = L Fio = 16 MHz, 50% Vcc 10 Test Conditions Duty Cycle = 50% Min -- -- Typ -- -- -- -- -- 1.0 -- -- 0.2 20 -- -- Max 20 20 55 10 10 -- 150 150 -- 1.0 -- 2.0 -- Unit MHz MHz % ns MHz ns -- s s s s *90% Vcc (8) 45 -- -- -- -- -- -- -- -- 2.0 10%-90% Vcc 50% Vcc, L-tH, H-uL Vcc Power Up/Down RES, VCC Power Up/Down (6) Pin Load = 30 pF (7) Since the clock buffer is optimized for low current consumption, clock signal duty cycle is guaranteed for divide by 2 and divide by 4 ratio. http://onsemi.com 7 MC33561 DIGITAL DYNAMIC SECTION @ Vbat = 5 V, Programming Mode(6) Symbol Tsmod Characteristic Data Set-up Time RDY_MOD, PWR_ON, RESET, I/O Data Hold Time RDY_MOD, PWR_ON, RESET, I/O CS Low Pulse Width Test Conditions Min 1.0 Typ -- Max -- Unit s Thmod 1.0 -- -- s Twcs 2.0 -- -- s DETAILED OPERATING DESCRIPTION Card Vcc and Card Clock Programming The CRD_VCC and ASY_CLK programming options allows matching the system frequency with the card clock frequency, and to select 3 V or 5 V CRD_VCC supply. The table 3 given hereafter highlight the PWR_ON, RESET and I/O values for the possible options. The default power reset condition is state 4: synchronous clock and CRD_VCC = 5 V. All states are latched for each output variable in programming mode at the positive going slope of CS. Table 3. Card Vcc and Card Clock Truth Table STATE # 0 1 2 3 4 5 6 7 PWR_ON L L L L H H H H RESET L L H H L L H H I/O L H H L L H H L CRD_VCC 3V 3V 3V 3V 5V 5V 5V 5V CRD_CLK SYN_CLK ASY_CLKIN/4 ASY_CLKIN/2 ASY_CLKIN SYN_CLK ASY_CLKIN/4 ASY_CLKIN/2 ASY_CLKIN NOTE: Card clock integrity is guaranteed no spikes whatever be the frequency switching. At power ON, state 4 is the default state machine. DC/DC Converter and Card Detector Status The MC33561 status can be polled when CS = L. Please consult Table 3 for a description of input and output signals. The status message is described in Table 4. Table 4. PWR_ON (Input) LOW LOW HIGH HIGH RDY_MOD (Output) LOW HIGH LOW HIGH No Card Card Present DC/DC Converter Overloaded DC/DC Converter OK Message http://onsemi.com 8 MC33561 APPLICATIONS INFORMATION +5V 2 +5V GND C11 22 pF C9 C10 22 pF GND 4 MHz R1 40 37 11 10 9 8 7 6 5 4 12 13 14 15 17 18 19 20 1M R3 2 41 39 1 31 32 33 34 35 36 38 30 29 28 26 25 24 23 22 16 27 10 k D2 1N4148 R2 47 k SW2 GND RESET J1 C8 220 nF +5 U3 MC33561 L1 47 mH GND GND 1 2 3 4 5 6 7 8 9 SW1 Card Detection CLK RST VCC GND I/O U2 MC7805K +5 V V in 1 J3 2 1 SUPPLY GND 3 D1 C1 100 nF Vz 40 V OSC2 IRQ TCMP OSC1 PA0 TCAP PA1 RST PA2 PD0/RDI PA3 PD1/TDO PA4 PD2/MISO PA5 PD3/MOSI PA6 PD4/SCK PA7 PD5/SS PB0 PD7 PB1 PC0 PB2 PC1 PB3 PC2 PB4 PC3 PB5 PC4 PB6 PC5 PB7 PC6 PC7 NC NC U4 GND 1 2 3 4 5 6 7 8 9 10 PWR_GND PWR_ON RDY_MOD CS RESET I/O SYN_CLK ASY_CLKIN INT 20 VBAT 19 Lout 18 17 CRD_DET 16 CRD_CLK 15 CRD_RST 14 CRD_VCC 13 CRD_GND 12 CRD_IO 11 DIG_GND CARD SLOT + C7 220 nF MC68HC705C9ACB(42) C6 22 mF GND 100 nF C3 1 12 MAX202 9 10 11 4 C4 5 6 C5 15 3 100 nF 2 U1 C2 16 13 8 7 14 GND 5 9 4 8 3 7 2 6 1 J2 RS232 Figure 3. Typical Application Schematic Diagram ORDERING INFORMATION Device MC33561DTB MC33561DTBR2 Package TSSOP-20 TSSOP-20 Shipping 75 Units / Rail 2500 Units / Tape & Reel http://onsemi.com 9 MC33561 PACKAGE DIMENSIONS TSSOP-20 DTB SUFFIX CASE 948E-02 ISSUE A 20X K REF M 0.15 (0.006) T U S 0.10 (0.004) TU S V S 2X L/2 20 11 B L PIN 1 IDENT 1 10 J J1 -U- SECTION N-N 0.25 (0.010) N 0.15 (0.006) T U S A -V- N F DETAIL E C D 0.100 (0.004) -T- SEATING PLANE G H DETAIL E http://onsemi.com 10 III III III M K K1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ -W- DIM A B C D F G H J J1 K K1 L M MC33561 Notes http://onsemi.com 11 MC33561 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION USA/EUROPE Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line*: 303-675-2167 800-344-3810 Toll Free USA/Canada *To receive a Fax of our publications ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5487-8345 Email: r14153@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. America Technical Support: 800-282-9855 Toll Free USA/Canada http://onsemi.com 12 MC33561/D |
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